1. Field of the invention
The present invention relates to a paging receiver system, and in particular to a clock generating method capable of executing a bit synchronization (SYNC) upon variation of receiving data.
2. General description of the art
FIG. 1 is a system block diagram of a paging receiver of a preferred embodiment of the present invention, which includes: an antenna 1 for receiving a modulation signal of data propagating on air; a RF receiving device 2 for demodulating a modulation signal through the antenna 1 and then reshaping the waveform into digital data; a control device 3 wherein data through the RF receiving device 2 is controlled and various control signals such as a power saving signal are produced; a memory 4 which stores frame data of 3 bits and an address of 16 bits for seeking data of its own among the input data, and which is read by the control device 3 upon an initial time of power on; and alarm device 5 for driving an alarm signal when the own frame data are sought under the control of the control device 3; a speaker 6 for producing an alarm sound according to the alarm signal through the alarm device; and a display device 7 for displaying a received message under the control of the control device 3.
FIGS. 2a-2d are format diagrams of POCSAG (Post Office Committee Standard Association Group) code among codes used in a paging receiver, wherein a POCSAG includes a preamble signal and a number of batches, a batch includes a word SYNC and 8 frames, a frame includes an address codeword of 32 bits and a message codeword of 32 bits, and a transmission speed is 512 bps.
FIG. 3 is a timing chart showing a generation of conventional data receiving clock, which shows that a clock is generated at a half position (1/2 T) of the receiving data bit.
The operational steps of a paging receiver utilizing the POCSAG code will be explained in accordance with the above-mentioned configuration. Generally, a paging receiver receives a RF (Radio Frequency) signal transmitted by modulating into FSK-NRZ (Frequency Shift Keying-Non Return to Zero) through an antenna 1, and RF receiving device 2 demodulates the RF modulation signal and then reshapes its output waveform into a digital signal of binary code. In addition, the memory 4, preferably a programmable ROM, stores a fixed own address of the paging receiver and the frame data, which constitute dual-address data. Therefore, when the control device 3 receives a message of POCSAG code as shown in FIG. 2, it receives a message of own frame according to the content of the memory 4. These processes are as follows: After detecting a preamble signal received prior to a number of batch message as (2b) in FIG. 2, a bit-synchronization (bit-SYNC) of data receiving clock is adjusted according to the preamble signal detected and the receiving data are checked. Further, after the control device 3 reads out the dual address stored in the memory 4, it stores to the RAM which is an internal memory and stores also an address codeword among the own frame data received as (2d) in FIG. 2 into the internal RAM. Thereafter they are read out and compared respectively at an accumulator ALU. Moreover, a message codeword among the own frame data is stored in a buffer memory of interior, and when the received data compared at the accumulator ALU are judged as proper data, an alarm tone is produced through the alarm device 5 and the speaker 6. At the same time, the corresponding message is displayed through the display device 7.
In a paging receiver as aforementioned a conventional clock generating system for data receiving utilizes either a clock generating method according to PLL (Phase Locked Loop) system as disclosed in U.S. Pat. No. 3,557,308 or another method as disclosed in U.S. Pat. No. 3,801,956 or U.S. Pat. No. 4,554,540, wherein a decoder circuit executes data recovery and clock generation by applying a multiple scan for each bit. Furthermore, there has also been disclosed a clock generating system for data receiving therein applying a simple timer other than the above systems. In such a conventional clock generating system for data receiving, there has been a problem that, in the former case, due to its complicated hardware construction, the integration becomes relatively difficult and the power consumption increases, and also the matching for bit SYNC in response to the variation of data its difficult when a duty period of input data is either changed or trembled at an area of much noise. Moreover, in the latter case, since a high speed clock had to be utilized, a current consumption was increased. And since the multiple scan had to be executed continuously at every data input after a bit is once synchronized, a duration of power supply was reduced. Furthermore, hardware size will be large by using the decoder circuit.